Pattern-Guided Adaptive Equalizer in 65nm CMOS

The use of adaptive equalizers at the front end of receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes [1], with the latter requiring less area and power. Previous non-data-aided adaptive schemes [2-3] implement an asynchronous analog algorithm where the power spectrum of the received signal is checked for balance around a threshold frequency. Similarly, [4] proposes a digital adaptive algorithm which is based on the detection of specific 5-bit patterns. In all three works [2-4], however, adaptation is provided only for equalizers with a single coefficient, which are suitable for well-behaved channels. In contrast, this paper presents a digital adaptive engine for an equalizer with two coefficients: one adjusting the equalizer gain at the Nyquist frequency (fN) and one at fN/2. Furthermore, the proposed engine is asynchronous; it can function when driven by a blind clock at the receiver. This is useful as it allows the adaptation process to start even when the CDR has not yet achieved lock. This also avoids a deadlock situation where the CDR and equalizer require simultaneous access to the equalized data and the recovered clock. Our measured results of the proposed adaptive equalizer in 65nm CMOS confirm that the adaptation converges to within 2.6% of the optimal vertical eye opening in less than 400μs for two different channels at a data rate of 6Gb/s with a 25,000ppm frequency offset.